Memory is utilized in modern computing architectures for storing data. One type of memory is Dynamic Random Access Memory (DRAM). DRAM may provide advantages of structural simplicity, low cost and high speed in comparison to alternative types of memory.
DRAM may utilize memory cells each having one capacitor in combination with one transistor (so-called 1T-1C memory cells), with the capacitor being coupled with a source/drain region of the transistor. An example 1T-1C memory cell 2 is shown in FIG. 1, with the transistor labeled T and the capacitor labeled C. The capacitor has one node coupled with a source/drain region of the transistor, and another node coupled with a common plate, CP. The common plate may be coupled with any suitable voltage, such as a voltage within a range of from greater than or equal to ground to less than or equal to VCC (i.e., ground≤CP≤VCC). In some applications, the common plate is at a voltage of about one-half VCC (i.e., about VCC/2). The transistor has a gate coupled to a wordline WL (i.e., access line), and has a source/drain region coupled to a bitline BL (i.e., digit line or sense line). In operation, an electrical field generated by voltage along the wordline may gatedly couple the bitline to the capacitor during read/write operations.
Another prior art memory cell 1T-1C memory cell configuration is shown in FIG. 2. The configuration of FIG. 2 shows two memory cells 2a and 2b; with memory cell 2a comprising a transistor T1 and a capacitor C1, and with memory cell 2b comprising a transistor T2 and a capacitor C2. Wordlines WL0 and WL1 are electrically coupled with the gates of transistors T1 and T2, respectively. A connection to a bitline BL is shared by the memory cells 2a and 2b. 
Another prior art memory cell configuration utilizes two transistors in combination with one capacitor. Such configuration may be referred to as a 2T-1C memory cell. A 2T-1C memory cell 4 is schematically illustrated in FIG. 3. The two transistors are labeled T1 and T2; and may be referred to as first and second transistors, respectively. The capacitor is labeled C.
A source/drain region of the first transistor T1 connects with a first node of the capacitor C, and the other source/drain region of the first transistor T1 connects with a first comparative bitline (BL-T). A gate of the first transistor T1 connects with a wordline WL. A source/drain region of the second transistor T2 connects with a second node of the capacitor C, and the other source/drain region of the second transistor T2 connects with a second comparative bitline BL-C. A gate of the second transistor T2 connects with the wordline WL.
The comparative bitlines BL-T and BL-C extend to a sense amplifier SA which compares electrical properties (e.g., voltage) of the two to ascertain a memory state of memory cell 4. The bitline BL-T may be referred to as a true bitline, and the bitline BL-C may be referred to as a complementary bitline. The terms “true” and “complementary” are arbitrary, and merely indicate that the bitline values of BL-T and BL-C are to be compared to one another.
Another prior art memory cell configuration utilizes two capacitors in combination with two transistors. Such configuration may be referred to as a 2T-2C memory cell. A 2T-2C memory cell 6 is schematically illustrated in FIG. 4. The two transistors of the memory cell are labeled T1 and T2, and may be referred to as first and second transistors, respectively. The two capacitors are labeled C1 and C2, and may be referred to as first and second capacitors, respectively.
A source/drain region of the first transistor T1 connects with a node of the first capacitor C1, and the other source/drain region of the first transistor T1 connects with a first comparative bitline BL-T. A gate of the first transistor T1 connects with a wordline WL. A source/drain region of the second transistor T2 connects with a node of the second capacitor C2, and the other source/drain region of the second transistor T2 connects with a second comparative bitline BL-C. A gate of the second transistor T2 connects with the wordline WL. Each of the first and second capacitors C1 and C2 has a node electrically coupled with a common plate CP.
The comparative bitlines BL-T and BL-C extend to a sense amplifier SA which compares electrical properties (e.g., voltage) of the two to ascertain a memory state of memory cell 6.
Another prior art memory cell configuration utilizes three transistors in combination with one capacitor. Such configuration may be referred to as a 3T-1C memory cell. A 3T-1C memory cell 8 is schematically illustrated in FIG. 5. The three transistors of the memory cell are labeled T1, T2 and T3; and may be referred to as first, second and third transistors, respectively. The capacitor is labeled C.
A source/drain region of the first transistor T1 connects with a write bitline WBL, and the other source/drain region of the first transistor T1 connects with the capacitor C. A gate of the first transistor T1 connects with a write wordline WWL.
A source/drain region of the second transistor T2 connects with a common plate CP, and the other source/drain region of the second transistor T2 connects with a source/drain region of the third transistor T3.
A gate of the second transistor T2 connects with the capacitor C.
One of the source/drain regions of the third transistor T3 is the source/drain region connected with the source/drain region of the second transistor T2, and the other connects with a read bitline RBL. A gate of the third transistor T3 connects with a read wordline RWL.
The memory cells of FIGS. 1-5 may be incorporated into memory arrays. The 1T-1C memory cells of FIGS. 1 and 2 may be utilized in memory arrays having open bitline arrangements, with the open bitline arrangements having paired bitlines which are compared with sense amplifiers. An example DRAM array 9 having open bitline architecture is shown in FIG. 6. The DRAM array 9 includes memory cells of the type described in FIG. 2 (not labeled in FIG. 6 in order to simplify the drawing), wordlines, WL(0-7), and comparative bitlines. The comparative bitlines include a first set BL-T(1-9), and a second set BL-C(1-9). Electrical properties of bitlines from the first set are compared with electrical properties of bitlines from the second set utilizing sense amplifiers, SA(1-9). The wordlines are coupled with wordline drivers.
It would be desirable to incorporate memory into three-dimensional arrangements having stacked memory array decks (i.e., tiers). However, such can be complicated due to wiring associated with each memory array deck needing to be extended to circuitry peripheral to the memory array deck. For instance, bitlines may need to extend sense amplifiers and/or other peripheral circuitry; and wordlines may need to extend to wordline drivers and/or other peripheral circuitry. It would be desirable to develop wiring arrangements (e.g., bitline/wordline arrangements) suitable for utilization with stacked memory array decks.